Tilera Crams 100 Cores Into Next-Gen Processors
Tilera has targeted its new family of multicore processors at cloud computing, enterprise networking, multimedia and wireless infrastructure functions. The largest of the chips will have 100 cores, the company claims. In order to avoid the data traffic jams that often plague massively multicore designs, Tilera's design uses a dynamic distributed approach instead of piling on more memory.
Multicore processor specialist Tilera has announced a new family of processors which includes what the company says is the first-ever 100-core processor.
The TILE-Gx family will have four processors, with 16, 36, 64 and 100 cores.
It is aimed at cloud computing, enterprise networking, multimedia and wireless infrastructure.
The 100-Core Processor
Tilera's processors are based on its iMesh architecture, which can scale to hundreds of RISC-based cores or more on a single chip. RISC stands for Reduced Instruction Set Computing.
The 100-core Tilera processor will have 200 terabits of mesh bandwidth, Bob Doud, Tilera's director of marketing, told TechNewsWorld. This will solve the main problem to scaling up the number of cores on a processor -- bandwidth.
"You can put 1,000 cores on a chip, but if you can't feed it from memory, all those cores are fetching data all the time and will suck up all your memory," Carl Howe, director of anywhere research at the Yankee Group, told TechNewsWorld.
The 100-core processor will also have 32MB of cache, Doud said. This will be a combination of L1 and L2 cache.
Instead of piling on core memory, Tilera uses a dynamic distributed approach. "Our caching technology is very scalable -- instead of having big centralized caches as Intel has, we distribute the caches among the tiles and we let tiles look into each others' caches in a coherent manner," Doud explained. "You can't just keep piling on bigger and bigger caches."
Tilera's "Cache for Home" technology does load balancing among caches, either across all the cores in a chip or in clusters of cores.
Mesh architecture is used most widely in wireless mesh networking. Each node in a mesh network can act as an independent router, whether or not it is connected to another network. This allows for continuous connections and reconfiguration around broken or blocked paths by "hopping" from node to node until the destination is reached.
"Think of it as the Internet on a chip," Doud said.
Tilera's chips have five meshes, Doud explained. One's for memory, one's for I/O (input/output), one's for cache coherency and two are in the user space. Mesh networking lets processors scale up their cores. It may let processors scale up to 1,000 cores, Doud said.
Tilera's processors are built on the concept of a tile, which consists of a processor core, a cache and a switch. The switch lets each tile mesh with its neighbors on all sides. "We draw the analogy of the Internet on a chip because each of these switches can route packets up, down, left and right, and they're scalable, whereas buses and rings don't scale," Doud said.
All the tiles are homogeneous and users can allocate them as desired to any task, Doud said. In essence, then, the tiles form a pool of resources which can be called up or returned to the pool at will. This is similar to the concept of maximizing the use of existing resources that lies at the heart of virtualization.
About the TILE-Gx Family
The TILE-Gx family is being fabricated using the Taiwan Semiconductor Manufacturing Company (TSMC)'s 40-nanometer process.
TILE-Gx processors operate at up to 1.5 GHz with power consumption ranging from 10 to 55 watts. The chips have integrated high-performance DDR3 memory controllers. Each chip has either two or four 72-bit controllers running at speeds of up to 2,133 MHz with error-correcting code (ECC) support.
The processors have hardware acceleration engines on-chip. These Multistream iMesh Crypto Accelerator engines deliver up to 40 GB/second encryption and 20 GB/second full duplex compression processing. This is tightly coupled to the iMesh for low latency and wire-speed throughput.
Wire-speed throughput is enhanced by multicore programmable intelligent packet engines. These provide wire-speed packet classification, load balancing and buffer management. The engine is flexible and programmable in the C language. It delivers 80 GB/second and 120 million packets per second of throughput for packets with multiple layers of encapsulation.
For enhanced security, the chips contain a high-performance true random number generator and public key accelerator. These enable up to 50,000 RSA handshakes per second.
Samples of the TILE-Gx36 processor will be available in the fourth quarter of 2010. The other processors will be rolled out in the following two quarters.
The More the Merrier
While Tilera is promising a 100-core processor, it is not the first company to scale up the number of cores on a chip beyond the 64 cores currently available.
"Back in 2007, Intel demonstrated other processors with many, many cores," Matthew Wilkins, principal analyst of computer platforms research at iSuppli, told TechNewsWorld. "The Intel Tera-scale was discussed as having 80 cores."
That, Doud said, was just a laboratory experiment. "The 80-core Tera-scale prototype used only floating point cores," he explained. "We believe Intel is probably four years away from having 100 cores."