IBM claims it has found a way to apply nanotechnology — a field of study in which researchers have manipulated materials at dimensions approaching the size of individual molecules — to producing semiconductor components with existing chip-making tools.
Big Blue researchers, who will present their findings at the IEEE International Electron Devices Meeting in Washington, D.C., this week, said they were the first in the industry to successfully apply the nanotechnology to conventional semiconductor processing. The result could be smaller, faster chips that can be created without the cost of new tools or the risks of changing processes.
The IBM researchers used a molecular self-assembly technique to form the critical features of a semiconductor memory device, in this case a variant of flash memory, and said pilot devices could be made with the technique in approximately three to five years.
“Self-assembly opens up new opportunities for patterning at dimensions smaller than those in current technologies,” said T.C. Chen, vice president of science and technology at IBM Research. “As components in information technology products continue to shrink toward the molecular scale, self-assembly techniques could be used to enhance [existing] lithographic methods.”
Shaping and Shrinking
IBM’s technique — which researchers have said could be used in microprocessors for computers and consumer devices — takes advantage of polymer molecules that organize themselves. The self-assembly technology is essentially a subset of the nanotechnology approach in which researchers tap individual elements that have a tendency to arrange themselves in regular, nanoscale patterns.
The polymer molecule pattern creates device features that are smaller, denser, more precise and more uniform than conventional semiconductor methods, according to IBM.
The technique adds to IBM’s work with nanotechnology in microelectronics, which includes patents on a magnetic storage formed from nanoparticles as well as other nanotechnology-based implementations.
In using the self-assembly method to create a semiconductor memory device, IBM relied on formation of a dense, silicon nanocrystal array that has become the basis for a variant of conventional flash memory, the company said.
While nanocrystal memories are difficult to fabricate using conventional methods, the self-assembly technique is easier to implement and less expensive, Big Blue said.
IBM also said it has tested and demonstrated the technique by performing device processing on silicon wafers using methods that are compatible with existing chip-making tools.
Proof of Process
IBM staff researcher Chuck Black, a leader on the project, told TechNewsWorld that the research team used flash memory because it was conducive to the polymer pattern, but the research has implications for other semiconductor components.
“While we don’t have any imminent plans — we’re not about to start making flash memory — the point is the process is in place and it does meet the criteria of compatibility and works with [existing] tooling infrastructure,” Black said. “Should the need arise, it can be integrated in without the difficulty that any other nanotechnology approach would have.”
Black said that because scaling problems are common among the many components of integrated circuits, IBM researchers have begun to look at other areas that could benefit from the new technique.
He said IBM researchers also are focusing on going even smaller as they contemplate shrinking the dimensions of the polymer patterns themselves.
IBM is not the only chip manufacturer searching for ways to smooth the evolution of computer chips that are becoming smaller and smaller to accommodate new size, power and efficiency requirements.
Last month, chip giant Intel announced it had discovered a new insulation, called high-k, for smaller future chips. Intel said that the breakthrough, which addresses the issue of memory leakage, would allow the company to continue releasing technology consistent with Moore’s Law, a theory named after Intel cofounder Gordon Moore that says the number of transistors on a chip will double every 18 months.
Gartner research vice president Martin Reynolds told TechNewsWorld that although such findings are true breakthroughs, the discoveries and announcements never feel like such because the technology does not come out for three or four years, when it might be viewed simply as another step in the Moore’s Law ladder.