Intel Beefs Up Front-Side Bus for Itanium 2 Chipset

By boosting the bandwidth of its front side bus (FSB), chip giant Intel is gradually improving performance of its Itanium 2 chips, laying the groundwork for the dual-core version of the microprocessor to come later down the road.

Intel said its latest Itanium 2 processors will have a 667 megahertz (MHz) front side bus — a silicon component that connects and transfers data among the processor, chipset and memory — and will thereby be capable of delivering 65 percent more bandwidth for servers designed for the chips, including new Hitachi BladeSymphony servers due out next month.

Analysts suggested that although Itanium and its adoption may have been less than promised from Intel in some regards, the processor is nevertheless progressing with improvements, some of which Mercury Research president Dean McCarron says are significant.

“It’s an important step,” McCarron told TechNewsWorld. “Basically it’s an indication of the improvement in processor performance and an indication Itanium is continuing to progress in terms of its performance.”

Itanium Milestone

Intel said its Itanium server processor was succeeding in displacing market share from mainframe, RISC and other non-Itanium-based high performance computing, as has been originally intended.

As for its latest Itanium 2 chips with the added FSB bandwidth — codenamed “Madison” — Intel indicated the enhanced technology allows for 10.6 gigabits of data per second to pass from the processor to other system components. The current generation 400 MHz FSB transfers 6.4 gigabits of data per second, Intel added, highlighting the ability to quickly move more data as “critical to compute-intensive applications in the scientific, oil and gas and government industries.”

While touting improvements in its Madison chips, Intel also referred to its coming “Montecito” Itanium 2 chips, expected to ship soon. The chips are enhanced to deliver twice the performance, as much as three times the system bandwidth, and more than two and a half times the on-die cache compared to current Itanium designs, Intel said.

“Looking forward, we are coming up on the next major milestone for the Itanium processor family — dual-core server platforms based on Montecito,” said a statement from Intel Server Platforms Group general manager Kirk Skaugen.

Bandwidth Boost

Mercury’s McCarron said the enhanced FSB bandwidth would deliver less of a pure performance improvement and more of an input/output (I/O) advantage, which is important in running applications.

“Because it’s in the front side bus, it’s not necessarily going to boost computational performance,” McCarron said. “It does greatly boost the I/O of systems and the systems Itanium goes into tend to be I/O intensive.”

Itanium has been touted as a technology to displace x86 processor architecture, but it has suffered somewhat from lower-than-expected sales and stiff competition from rival AMD’s Opteron chips. McCarron said Itanium has done well with mainframe and RISC replacement, however.

“I think there were a lot of unrealistic expectations for Itanium,” he said. “It was intended to compete with mainframes and RISC. In that context, it’s doing well.”

Laying Groundwork

As for the latest FSB improvements, McCarron said they deliver a gradual performance gain, but more importantly, they pave the way for the dual-core Itanium 2.

“It lays an important infrastructure for the dual-core products that are coming later,” he said, adding that performance gains with the forthcoming dual-core Itanium 2s will also be more significant.

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